In the manufacture of electronic components it is customary to mount one or more semiconductor chips on a substrate. The substrate provides a supporting and protecting structure for the relatively delicate chip while also bringing the relatively closely spaced electrical contacts on the chip out to a set of contacts on the substrate which are positioned in a more convenient arrangement for making connections to points external to the chip-carrying substrate. Such contacts are known for example as a pin grid array, surface mount contacts, and ball grid array contacts. It is often advantageous if a single chip design can be mounted on more than one particular substrate. For example a specialized ASIC chip might be mounted in a ceramic pin grid array with heat sink and operated at a high clock rate and high power for one application. For another, perhaps portable, application the same chip may be mounted on an organic ball grid array carrier and operated at low speed and low power. In other applications, a video encoder or video decoder ASIC chip for example, may be mounted in a variety of packages depending on the application.
It is particularly advantageous in some applications for the electronic circuits on the chip to be able to sense a variety of conditions unique to the application including what package type it is mounted in, a desired operating speed, or power level. Consequently one or more input pins are connected externally or within the package to a power or ground point as a way of indicating such conditions.
It is known to decode one of two conditions at a single input by determining whether the input is at a first or second logic state. Furthermore it is known that by corresponding use of N inputs, a total of 2 to the N.sup.th power (2.sup.N) conditions can be determined. Cornell et al, in U.S. Pat. No. 4,721,868, for example, describes a scheme for indicating 2.sup.N conditions by connecting each of N inputs to ground through a programmable fuse. Programming circuitry can then selectively "blow out" fuses on specific inputs allowing those inputs to rise to a second logic state while other inputs remain connected to ground.
In many applications, particularly for ASIC chips, the total number of external connections is limited by the number of bond pads or C4 pads on the chip. While progress in semiconductor chip processing has dramatically increased the amount of circuitry which can be placed on a chip, the number of bond pads has increased only slightly over the same time period. As a result, the number of available bond pads has become a limiting factor with each becoming a valuable resource. The number of bonds pads devoted to sensing the type of conditions described above must therefore be kept to an absolute minimum.
A method which increases the number of conditions which can be sensed using N inputs would therefore represent a significant advance in the art of semiconductor application design.
In U.S. Pat. No. 5,023,483, May describes an apparatus and method for decoding four conditions with one pin. The four conditions involve connecting the pin to either a first or second logic state using either a high or low value of resistance. Rather complex circuitry involving memory, an isolator circuit, default circuit, read circuit and write circuit then attempt to drive and sense the logic state of the pin. When a high value of resistance is used for the connection, it is possible to drive the pin to the opposite logic state from the state to which it is connected, by use of a sufficiently powerful driver which can overcome the high value of resistance. When a low value of resistance is used for the connection, then the driver cannot overcome the effect of the resistor and it is not possible to drive the pin to the opposite logic state. These four conditions can therefore be determined through use of the complex circuitry and methods described by May.